1. Field of the Invention
The invention is directed to a method for the continuous and interruption-free readout of a data sequence from a memory, the memory being of a type having a number of separately addressable memory banks.
2. Description of the Prior Art
There are numerous applications in digital technology in which a continuous digital data stream must be generated, for example in the case of a digital word generator or a so-called ARB signal generator, from which the data stream is subsequently supplied to a digital-to-analog converter. The data to be supplied as an output are usually generated either on a computer or read in via an interface and stored in an output memory. They are then read out from this memory with a desired clock rate.
Hitherto, such output memories have usually been implemented as static memories, known as SRAMs. Such memories have the disadvantages that they are not as highly integrated as the otherwise standard dynamic memories (DRAMs) and that they are relatively expensive for larger datasets.
Dynamic memories are not suitable for the continuous readout of a data stream since they cyclically require a refresh. If this refresh is omitted, the memories lose their contents. The refresh lasts longer than a normal memory access. This is the reason that a continuous and uninterrupted data stream, whose speed or rate lies on the order of magnitude of the access time, cannot be generated with such dynamic memories. For this reason, such dynamic memories have been employed only in computers wherein the program execution is cyclically interrupted, and thus there is time for a refresh of the entire memory.
This is also true of a known memory arrangement that operates with synchronous dynamic memory elements (SDRAM) (Bursky, "Fast Drams Can Be Swapped For Sram Caches", Electronic Design 22, Jul. 22, 1996, pages 55 to 70). Such a memory is divided into two separate memory banks, and the control circuit that controls the readout of the data sequence from the memory cells of the two memory banks is fashioned such that another bank is refreshed during the readout of data from one of the banks. This known memory, however, also requires a pause having the length of a clock at the sequence end, since the refresh of the other bank is not yet completed at the end of the access to the one bank (FIG. 5, page 64, pause between Dn8 and Qp1 in the aforementioned Electronic Design article). Thus, a continuous and interruption-free readout of a data sequence is also not possible with this known memory.